FinFET generally refers to a nonplanar, double-gate transistor. Integrated circuits that include FinFETs may be fabricated on a bulk silicon substrate or, more commonly, on a silicon-on-insulator (SOI) wafer that includes an active SOI layer of a single crystal semiconductor, such as silicon, a semiconductor substrate, and a buried insulator layer, e.g., a buried oxide layer that separates and electrically isolates the semiconductor substrate from the SOI layer. Each FinFET generally includes a narrow vertical fin body of single crystal semiconductor material with vertically-projecting sidewalls. A gate contact or electrode intersects a channel region of the fin body and is isolated electrically from the fin body by a thin gate dielectric layer. At opposite ends of the fin body are heavily-doped source/drain regions. Conventional methods of forming the fin body utilize subtractive techniques in which a uniform thick layer of single crystal silicon is patterned by masking and etching with processes like reactive ion etching (RIE).
In FinFET manufacturing processes, the fins are merged together by a selective epi Si grown around each of the fins. The epi Si growth is critical to the merging of the fins. After the formation of the selective epi Si to merge the fins, a final spacer is formed and a source/drain (S/D) implant is performed though the epi Si to implant the fins with a dopant. A silicide is then formed over the implanted epi Si.
The selective epi Si growth process, though, is difficult to control and hence is unstable. Because of this difficulty, the epi Si may grow to different thicknesses on individual fins on the same wafer or between processing runs of different wafers, for example. Thus, this inconsistent growth can result in the epi Si being thicker or thinner than designed thus leading to device degradation. For example, when the epi is too thick, the dopant may not reach the fin, itself, or be at a lower than desirable level, resulting in high resistance. This high resistance, of course, degrades the device performance. On the other hand, when the epi Si is too thin, the implant will amorphize or damage the fin. In this case, the annealing process will not crystallize the fin and resistance will remain high. Again, this high resistance degrades device performance. Furthermore, as diameter of the Fin, DFin, approaches to approximately 6 nm as gate scaling demands for future nodes, selective epi merging technique may not be possible.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.